1. Field of the Invention
The present invention relates to operational amplifiers, and more specifically to a circuit and method for compensating the offset voltage at the output of an operational amplifier.
2. Description of Related Art
A conventional operational amplifier is an analog (i.e., linear) circuit which can amplify voltages with a very high gain (e.g., 10,000 or more). It produces at its output a voltage which is proportional to the potential difference presented at its two inputs, which are known as the inverting and non-inverting inputs. The amplified voltage output is delivered at low impedance, so it is possible to drive relatively high loads without incurring significant stability losses. Conversely, the inputs exhibit a very high impedance, so as to allow weak signals to be amplified. Because of these advantageous characteristics, operational amplifiers are very widely used as basic elements in electronic circuits, such as drive, filtering, sampling, signal conversion (e.g., between analog and digital), and measurement circuits. They are also used as a virtual ground (i.e., to form a node in a circuit that exhibits a zero or fixed voltage without current consumption).
Operational amplifiers are generally constructed in the form of integrated circuits. In a typical application, several separate operational amplifiers can be integrated on a common substrate with numerous other circuit elements, which can be both analog and digital. For instance, a very large scale integration (VLSI) integrated circuit can include several tens of operational amplifiers, digital-to-analog converters, memories, a microprocessor, and the like to form a specific functional unit such as a control loop. An operational amplifier can be constructed with either bipolar transistors or field effect transistors, such as MOS transistors. There now exist operational amplifiers made using CMOS technology which can operate at very low voltages (e.g., on the order of 2V). Amplifiers made using CMOS technology can be integrated on a common substrate with digital CMOS circuits.
FIG. 1 shows a simplified circuit diagram of a conventional CMOS operational amplifier. This operational amplifier is based on a two-stage architecture having a differential input stage and a gain stage. In this amplifier, the gain stage also constitutes the operational amplifier""s output stage. The active elements of the differential input stage are formed by two NMOS transistors Q1 and Q2, which constitute a differential pair. The control gates of transistors Q1 and Q2 are connected to the inverting input EI and the non-inverting input ENI, respectively.
The differential input stage is connected to a load in the form of a current source that is formed by two PMOS transistors Q3 and Q4, which are connected to form a current mirror. The gain stage includes a PMOS transistor Q5 and its active load formed by transistors Q7, Q8, and Q9. The operation of the current sources is established by an input or a fixed reference current EIref. Conventionally, a compensation for the characteristics between the open loop and closed loop modes is obtained by a pole sharing capacitor C. Since the amplifier is given a unitary gain, this capacitor C is coupled between the output S and the gain stage input.
In principle, because an operational amplifier amplifies a difference in voltage between its two inputs EI and ENI, the voltage VO at the output S should be zero when these inputs are at the same potential (for example, by being connected together). However, in practice, an operational amplifier exhibits a spurious output voltage known as the offset voltage when there is no potential difference between the two inputs EI and ENI. This offset voltage is due to an imbalance between the characteristics of the amplifier""s respective inputs EI and ENI. Thus, the offset voltage is a component of the output signal which distorts the operation of the operational amplifier relative to its theoretical characteristics.
In the CMOS technology circuits currently being used for digital applications by virtue of their low current consumption, it is often necessary to bring together on the same substrate analog circuits such as differential amplifiers with purely digital circuit elements. At present, the use of operational amplifiers in logic circuits, especially in CMOS technology, is limited by non-uniformities in the transistor characteristics, which are linked to fabrication processes. Although tolerable with logic circuits which operate in a binary mode, these non-uniformities give rise to relatively large offset voltages (e.g., on the order of 5 to 10 mV in the case of operational amplifiers).
Techniques exist for calibrating an operational amplifier so as to reduce the offset voltage. Such zero-setting techniques consist in biasing one of the inputs EI or ENI of the amplifier (or more often an intermediate stage downstream of these inputs) with a fixed compensation voltage. This compensation voltage is set so as to re-balance the amplifier""s inputs EI and ENI so that the output voltage V0 is substantially equal to zero when the inputs EI and ENI are at the same potential. A first conventional operational amplifier zero-setting technique consists in periodically alternating the amplifier""s operating mode between a measurement phase and a normal operating mode phase. During the measurement phase, the two inputs EI and ENI of the operational amplifier are connected together so as to bring them to the same potential, and the amplifier""s offset voltage S is detected (e.g., by a sample-and-hold circuit). This offset voltage is used to produce a compensation voltage applied to a compensation input of the amplifier.
FIG. 2 shows an exemplary circuit for resetting to zero the offset voltage by using a sample-and-hold circuit. A switch 2 is connected to one of the inputs (ENI) of the operational amplifier 1 to connect that input selectively either to an external input voltage Vin in the normal operating mode (position P1), or to the amplifier""s other input (EI) during the measurement phase (position P2). A reference voltage source VS1 just before the EI input of the amplifier 1 serves to set the two inputs ENI and EI to the same potential during the measurement phase. During the measurement phase, the switch 2 is positioned at position P2 to disconnect the ENI input from its external input signal Vin and to set the amplifier""s two inputs EI and ENI to the voltage Vref of voltage source VS1. The voltage at the amplifier""s output S then corresponds to the offset voltage. This voltage is zeroed by applying a compensation voltage at an intermediate input N of the amplifier 1.
For this purpose, a feedback circuit is provided between the output S and the intermediate input N of the amplifier 1. In this exemplary amplifier, the feedback circuit includes a sample-and-hold circuit 4 whose input receives the output signal of the amplifier 1 via a buffer amplifier 6 and whose output is connected to the intermediate input N. The feedback circuit 4 and 6 serves to provide the right correction voltage at the intermediate input N by successive samplings. When this correction voltage is obtained, the switch 2 is set to position P1 to allow the amplifier to operate in the normal mode. However, the operational amplifier cannot fulfil its normal function of amplifying the signal Vin during this measurement phase.
The sample-and-hold technique can be replaced by a digital approach as shown in the exemplary amplifier of FIG. 3. The connections and operation at the inputs ENI and EI of the amplifier 1 are identical to those of the amplifier of FIG. 2. However, the sample-and-hold circuit 4, which is essentially analog in nature, is replaced by a digital register 8 and a digital-to-analog converter 10. During the measurement phase (with the switch 2 at position P2), the digital register 8 successively records at each cycle of a clock Clk a digital value corresponding to the offset value at the output S of the amplifier 1.
These values are converted into analog voltages by the converter 10 and then inputted at the intermediate input N of the amplifier. Thus, there is obtained a new value at the intermediate input N at each clock cycle, and this converges to the required correction value. For a more detailed description of such conventional operational amplifier output correction techniques, reference is made to C. Enz and G. Temes, xe2x80x9cCircuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilizationxe2x80x9d, which is published in Proceedings of the IEEE, vol.84, No. 11, November 1996, pages 1584 to 1614, which is herein incorporated by reference.
Offset voltage correction techniques based on sample-and-hold such as those described with reference to FIG. 2 have the drawback of requiring periodic reiterations of the measurement phase (with the switch 2 at position P2) in order to renew the correction voltage. In particular, the correction voltage is stored in a capacitor which loses its charge over time. As a result, the sampling technique can only be used in applications such as in comparators for analog-to-digital converters which can handle a periodic interruption of the operational amplifier""s normal operating mode to perform a measurement phase.
It is possible to overcome this problem of interruption by providing two operational amplifiers that are corrected in their offset values and operate in a shared mode on a common amplification channel. In such a case, an output switch alternately sends the output signal of each amplifier on the output channel during a limited period of normal operation. This solution has the drawback of introducing switching noise on the output channel. Moreover, the corresponding circuit increases the output impedance and requires twice the chip area of a single amplifier channel.
Furthermore, the offset correction by an external digital circuit such as that described with reference to FIG. 3 is relatively complex to implement both with regard to the associated digital elements and the algorithms used.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide an operational amplifier having at least one signal correction element that can be selectively put into circuit to add an offset voltage correction signal to the signal supplied to the output stage. The correction element or elements re-balance the characteristics of the two input channels so that the voltage offset is substantially zeroed. Thus, each element acts like a trimmer in association with the corresponding transistor.
Another object of the present invention is to provide an operational amplifier having means for determining the output voltage of the operational amplifier, means for applying a reference voltage to one of the inputs of the operational amplifier, means for selectively connecting the inputs of the operational amplifier, and programming means for programming the placing into circuit of at least one signal correction element of the operational amplifier.
Yet another object of the present invention provides a method of correcting the offset voltage of an operational amplifier in which an offset correction signal is determined by an iteration of cycles. According to the method, the offset voltage is measured, and then one or more signal correction elements are put into circuit to add the offset voltage correction signal in order to balance the characteristics of input channels of the operational amplifier.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.